The present invention relates generally to data transmission systems, and more particularly to high speed data transmission systems in which data values may be transmitted with a clock signal.
The increasing need for faster data communication rates has led to corresponding needs for faster transmission of data between system components. Networking hardware is but one of the numerous applications in which such increased speed is needed. Within a high-speed router data is typically transmitted between one or more integrated circuits. If such inter-chip data transmission speeds can be increased (e.g., in the range of 1 gigabits/second per pin), the overall speed/bandwidth of the connection between integrated circuits may also be increased.
Data transmission systems can include bus connections, in which bus lines may be commonly shared between multiple devices, and point-to-point connections, in which a one device is connected to another by one or more direct data transmission lines. Bus oriented systems may have a number of drawbacks. Due to the number of devices attached to the bus lines (because they are shared among multiple devices) the inherent capacitance attached to the lines may be large, limiting the speed at which the lines may be driven. Larger lines may consume higher amounts of power, as well. Still further, because a bus is commonly shared, some form of arbitration is typically included to enable one device to have control of the bus at a given time. Such arbitration needs can add to the complexity of the system. It is also noted that the inclusion of a common bus on a circuit board, or the like, requires a dedicated amount of area. This can work against the goal of manufacturing systems that are as physically compact as possible.
Bus and point-to-point approaches may have common drawbacks. One such drawback is susceptibility to xe2x80x9cground bounce.xe2x80x9d Ground bounce may occur due to sudden current draws on a power supply. In arrangements where signal lines are situated over a ground plane, rapid fluctuations in current may result in noise radiating from such a ground plane. In addition, or alternatively, due to inherent inductance in a power supply, a rapid fluctuation in current can cause a ground or supply voltage to vary (i.e., bounce). This may adversely affect data sensing operations that may depend on a stable supply voltage, or reference voltages generated from such supply voltages.
Yet another common drawback can arise in cases where a system includes differential type receiver circuits that rely on a reference voltage to distinguish between logic values. Circuits for generating such reference voltages can be complex. xe2x80x9cBand-gapxe2x80x9d reference voltage generators, and the like, represent but one example of a more complex reference voltage generating circuit. In many cases, reference voltage generating circuits must be designed to account for temperature, process and other variations. In addition, in many cases such circuits can be dependent upon a particular supply voltage (i.e., are not supply voltage independent).
Typically, transmission systems can rely on some sort of clock (or strobe) signal to extract information from a data signal. Clock signals may be supplied separately, or may be encoded within a data signal. A drawback to encoded data signals can be ancillary circuitry that may be necessary. As but one example, in many cases a phase lock loop (PLL) may have to be included to recover an embedded clock, and thereby enable data to be extracted. Still further, a data stream for a signal with an embedded clock may require a certain number of transitions within a given time period.
Various conventional examples will now be described with reference to a number of figures. Referring now to FIG. 18, a conventional data transmission system, that includes a serial to parallel conversion step, is shown in a block diagram and designated by the general reference character 1800. A system 1800 may receive one or more input lines 1802-0 to 1802-n on which data may be transmitted in serial form. Such serial data may include an embedded clock. Serial data may be stored in corresponding storage circuits 1804-0 to 1804-n, or like. Once a predetermined number of bits have been accumulated, such bits may be transmitted, in parallel from such storage circuits (1804-0 to 1804-n) onto parallel output lines 1806-0 to 1806-n. In addition to the various drawbacks described above, a conventional system 1800 also introduces the undesirable delay involved in converting serial data to parallel form. More particularly, a conversion to 8 parallel bits can require an 8 cycle latency.
Another conventional approach is shown in FIG. 19. FIG. 19 shows a conventional system 1900 in which data may be transmitted in parallel along input lines 1902-0 to 1902-n. Each input line (1902-0 to 1902-n) may be received at the input of a corresponding differential amplifier (1904-0 to 1904-n). Differential amplifiers (1904-0 to 1904-n) may distinguish between logic levels by amplifying differences between a reference voltage and an input line potential. A drawback to a parallel approach, such as that shown in FIG. 19, can be susceptibility to noise effects due to ground bounce, or the like. More particularly, a large majority of data signals may have the same logic level, generating a fluctuation in current and the corresponding adverse consequences noted above.
Additional drawbacks to a conventional case such as that shown in FIG. 19 can be the difficulty in generating a robust reference voltage.
Referring now to FIG. 20, a block diagram of a third conventional 2000 case is shown. A system according to a third embodiment may include a transmitting driver 2002 that can drive an input line 2004 between a voltage Vdrive and ground. An input line 2004 may be provided to one input of a receiving differential amplifier 2006. A second input to differential amplifier 2006 can be a reference voltage Vref, which may be ideally Vdrive/2. Termination resistance Rtx and Rrx may also be included to meet predetermined line impedance values for minimizing adverse transmission line effects.
The example of FIG. 20 may include some of the same drawbacks as that of FIG. 19. In particular, having unbalanced data values may generate noise, and the generation of a reference voltage may be complicated and/or not necessarily supply independent.
In light of the above, it would desirable to arrive at a data transmission system that may transmit data between two points without incurring the drawbacks of ground bounce noise and/or similar adverse effects. It would also be desirable to arrive at a system that is not subject to the constraints of conventional systems that may employ a separately generated reference voltage.
It would also be desirable to arrive at a data transmission system that may meet other additional capabilities.
An important system capability can be the ability to test a system or component for certain parameters. That is, while various system components may include particular operating specifications, once such components are assembled it can be difficult to test the operation of such systems. In a data transmission system, it can be valuable to determine how a system or component may operate under adverse condition that can result in additional noise and/or variations in a reference voltage. However, it can be difficult to introduce such conditions in order to actually test a system or component.
In systems that can operate according to a clock signal, an important feature can be the ability to determine signal skew. Signal skew, as related to data transmission systems, can include differences between a data value transition and an ideal transition, such as that of a clock signal. Determining signal skew of a system may allow for a system to be adjusted for better performance, and allow for a better understanding of the operational limitations of a system.
Thus, in light of the above discussion, it would be desirable to arrive at a data system that may allow for easier testing and/or provide a better way of measuring signal skew.
In many conventional approaches, data may be encoded prior to transmission and decoded upon reception. Encoding can improve the reliability of a data transmission by enabling easier clock recovery and/or reducing a xe2x80x9cDC componentxe2x80x9d of a transmission. In the case of binary transmissions, a DC component can be derived by adding for every xe2x80x9c1xe2x80x9d and subtracting for every xe2x80x9c0xe2x80x9d. Thus, as is well understood, the binary word 0000 1111 has a DC component of zero, while the binary word 1111 1111 has a DC component of eight. In serial communications, high DC components can lead to signal xe2x80x9cwanderingxe2x80x9d and thus erroneous transmissions. In parallel communications, high DC components can contribute to ground bounce effects and result in higher power consumption.
The present invention includes a data transmission system and method of encoding data that may generate clock inclusive low DC component encoded values. Clock inclusive encoded values may rely on a strobe signal value to offset DC components of certain encoded data values.
According to one aspect of the invention, encoded values may be essentially DC balanced with respect an entire encoded value, and with respect to a portion of an encoded value. More particularly, an 8-bit data value may be encoded into a 10-bit encoded value. Such a 10-bit encoded value may include two 5-bit portions that are essentially DC balanced themselves.
According to another aspect of the embodiments, encoded values may have one value corresponding to one strobe value, and a complementary value according to another strobe values.
According to another aspect of the embodiments, encoded values may have clock inclusive coding having DC components greater than xe2x88x922 and less than +2. In one particular arrangement, encoded values corresponding to a high strobe value may have DC components no less than xe2x88x922 or greater than 0. That is, the number of zeros may not exceed the number of ones by more than two. Encoded values corresponding to a low strobe value may have DC components no greater than 2 or less than 0. That is, the number of ones may not exceed the number of ones by more than two.
According to another aspect of the embodiments, encoded data values and a strobe signal may be transmitted over data lines between a transmitting portion and a receiving portion. A receiving portion may include a number of differential receiver circuits that receive a reference voltage. A reference voltage may be generated by a virtual center tap arrangement that may sum incoming encoded data values and a strobe value to generate a reference voltage.
According to another aspect of the embodiments, portions of a data value may be received in parallel and encoded by different encoding sections. Encoded values from different encoding sections may then be interleaved with one another and transmitted.
According to another aspect of the embodiments, encoded data values may be received in an interleaved fashion and decoded by different encoding sections. Decoded values may then be output in parallel to form a single output data value.
According to another aspect of the embodiments, clock inclusive low DC component encoded data values may be transmitted by point to point transmission lines from a transmitting portion to a receiving portion. Termination impedance may be provided to minimize signal reflectance.
According to another aspect of the embodiments, encoded data values may include control values. Control values can include idle values that are essentially DC balanced. Control values may further include stress codes that are not essentially DC balanced. Stress codes may generate higher noise environments and/or generate reference voltages that are higher than or lower than an optimal value.
According to another aspect of the embodiments, a control codes may be applied that place data lines at the same value for more than one strobe cycle, and then transition all data lines simultaneously. Such a transition can allow for better skew evaluation.